1. Field of Invention
The present invention relates to a semiconductor device and a fabricating method therefor, and more particularly to a capacitor and a fabricating method therefor in an manner that prevents the occurrence of lifting between a polysilicon pattern and a blocking metal layer of an upper electrode in the process of a wire-bond attached chip capacitor (hereinafter referred to as WACC).
2. Description of the Prior Art
A wire-bond attached chip capacitor (WACC) is mounted to an integrated circuit (IC), or chip, for enhancement of stable operation. The WACC is coupled to the IC by wire-bonding pads respectively positioned between the IC components and the WACC.
Generally, the WACC has been widely deployed in the power supply of semiconductor devices and other electronic devices. FIGS. 1a through 1d are diagrams for illustrating sequential processes of a conventional WACC fabrication method. With reference to the drawings, the method for fabricating the conventional WACC will now be described in detail.
As shown in FIG. 1a, a first insulating layer 12 of an oxide layer is formed on a p++ type silicon substrate 10. The first insulating layer 12 is selectively etched to expose an active area of the substrate 10. Accordingly, the substrate 10 of the active area positioned at the upper electrode is selectively etched to a predetermined thickness to form a plurality of trenches (t) in the substrate 10.
As shown in FIG. 1b, an oxide-nitride-oxide (ONO) dielectric layer 14 is formed on the resultant structure of FIG. 1a. A polysilicon layer 16 is constructed in a deposition structure comprising an undoped polysilicon layer 16a below a doped polysilicon layer 16b (referred to herein as an xe2x80x9cundoped/dopedxe2x80x9d structure) formed over the dielectric layer 14. At this time, the undoped polysilicon layer 16a is formed at a thickness of 500 Angstroms (hereinafter referred to as A) at 620xc2x0 C., while the doped polysilicon layer 16b is formed at a thickness of 2500 A at 540xc2x0 C. The purpose of the xe2x80x98undoped/dopedxe2x80x99 doubly layered structure in the polysilicon layer 16 is because the trenches t are formed for fabricating a capacitor to increase its effective area in designing a semiconductor device in accordance with a design rule of less than 0.25 xcexcm. Relying on solely the application of a general impurity impregnation process, it would be difficult to impregnate enough impurity to the upper end of the polysilicon layer 16.
As shown in FIG. 1c, the polysilicon layer 16 is removed, save the region of the upper electrode forming portion, so as to form a polysilicon pattern 16xe2x80x2. In the aforementioned process, the top oxide layer of the ONO dielectric layer 14 is also removed, causing thinning of the resultant dielectric layer 14. Accordingly, any remaining dielectric layer 14 remaining beyond the portion covered by the polysilicon pattern 16xe2x80x2 is eliminated. In order to make an ohmic contact between a blocking metal layer (a layer to be deposited during the next step) and the active area, p+ type impurity 24 is ion-impregnated in blanket onto the structure. As a result, a p+ type impurity diffusion area 18 is formed in the substrate 10 in the active region positioned at one side of the polysilicon pattern 16xe2x80x2.
As shown in FIG. 1d, the blocking metal layer is formed and annealed over the surface constructed by the previous processes, and an aluminum layer is, then, formed thereon. As a result, a first metal layer of a xe2x80x9cblocking metal layer/aluminum layerxe2x80x9d deposition structure is formed. For example, the blocking layer may comprise a xe2x80x9cTi/TiNxe2x80x9d deposition structure, wherein Ti is formed in thickness of 150 A and TiN is formed in thickness of 1000 A. The Ti of the blocking metal layer forms a silicide layer by reacting with the lower silicon (named for the combination of the polysilicon pattern and p++ type silicon substrate) in the annealing process, so as to improve adhesion between the blocking metal layer and silicon. TiN of the blocking metal layer prevents diffusion of the aluminum layer into the silicon in the deposition of the first metal layer. Accordingly, the first metal layer is selectively etched to expose a predetermined part of the first insulating layer 12, thereby respectively forming a first metal pattern 20a to be connected with the polysilicon pattern 16xe2x80x2 and a first metal pattern 20b to be connected with the p+ type impurity diffusion area 18. Then, a second insulating layer 22 made of an oxide layer as inter-layer insulating material is formed on the first insulating layer 12 that includes the first metal patterns 20a, 20b. A via hole (h) is then formed by selectively etching the second insulating layer 22 to expose a predetermined portion of the first metal pattern 20b connected with the p+ type impurity diffusion area 18. Finally, the second metal pattern 24 is formed on the second insulating layer 22 that includes the via hole (h), thereby completing the fabrication process.
As shown in FIG. 1d, a WACC is thus fabricated in the structure having an upper electrode (I) on its top portion, in which the polysilicon pattern 16xe2x80x2 and the first metal pattern 20a are connected with the dielectric layer 14 positioned therebetween, and a lower electrode (II) on its bottom portion, in which the first metal pattern 20b and the second metal pattern 24 are connected with the p++ type substrate 10.
As a consequence of the above process, however, the fabricated WACC suffers from a number of limitations. For example, adhesion between the silicon and the upper blocking metal layer is determined by the degree to which the Ti and silicon react during the annealing process. The thickness of the resultant layer (for example the silicide layer) is generally known to be inversely proportional to the doping level of the lower silicon layer. In other words, if the impurity doping level of the lower silicon is high, the reacted layer becomes thinner. If the impurity doping level of the lower silicon is low, the reacted layer becomes thicker. In this configuration, the lower silicon layer indicates all of the polysilicon pattern 16xe2x80x2 and the p++ type substrate 10.
Thus, in order to improve adhesion between Ti and silicon, the thickness of the reacted layer should be higher than a predetermined level thereof by lowering the impurity doping level of the lower silicon.
However, when the WACC is fabricated according to the aforementioned processes, the polysilicon layer is constructed in the xe2x80x9cundoped/dopedxe2x80x9d double deposition structure. As a result, in addition to the high doping level of the polysilicon layer, the impurity doping level of the polysilicon pattern 16xe2x80x2 becomes much higher by the blanket ion-impregnation of p+ type impurity, which has been additionally formed to make an ohmic contact. For this reason, the silicide layer is marginally formed between the polysilicon pattern 16xe2x80x2 and the blocking metal layer. As a consequence, a problem arises in that adhesion between the polysilicon pattern 16xe2x80x2 and the blocking metal layer of the upper electrode becomes weak, thereby resulting in the phenomenon of lifting therebetween.
It is therefore an object of the present invention to address the aforementioned limitations by providing a WACC having an upper electrode with its polysilicon layer constructed in a triply-layered deposition structure of xe2x80x9cundoped/doped/undoped polysilicon layersxe2x80x9d to enable the polysilicon layer contacting the blocking metal layer to be the undoped polysilicon layer. In this manner, an effective suicide layer is formed between the polysilicon layer and the blocking metal layer to reinforce adhesion and prevent occurrence of lifting therebetween.
It is another object of the present invention to provide a method for fabricating a capacitor that helps to effectively produce the semiconductor device constructed in the aforementioned structure.
In order to accomplish the aforementioned object of the present invention, there is provided a capacitor having a lower electrode, a dielectric layer and an upper electrode, wherein the upper electrode is constructed in a deposition structure of xe2x80x9cfirst undoped polysilicon layer/doped polysilicon layer/second polysilicon layerxe2x80x9d.
In order to accomplish the other object of the present invention, there is provided a method for fabricating a capacitor having lower electrode, dielectric layer and upper electrode, wherein the upper electrode is formed in a deposition structure comprising a xe2x80x9cfirst undoped polysilicon layer/doped polysilicon layer/second undoped polysilicon layerxe2x80x9d.
It is preferred that the first and second undoped polysilicon layers be formed at a thickness of less than 1000 A, the doped polysilicon layer be formed in thickness of 1800-2500 A, and the second undoped polysilicon layer be formed under the same temperature as that of the doped layer without any breakup of vacuum after formation of the doped polysilicon layer.
It is further preferred that the capacitor be designed to have a metal pattern in a deposition structure comprising xe2x80x9cblocking metal layer/aluminum layerxe2x80x9d. The blocking metal layer is preferably constructed in a xe2x80x9cTi/TiNxe2x80x9d deposition structure.
In the WACC thus fabricated, the blocking metal layer is contacted with an undoped polysilicon layer, rather than a doped polysilicon layer as in the conventional embodiment, to achieve the effect of reducing the doffing level of the polysilicon layer to lower than that of the conventional embodiment. This configuration significantly improves effectiveness in formation of a silicide layer between the polysilicon layer and the blocking metal layer, and prevents the occurrence of lifting therein.